The present invention relates to detection of semiconductor device defects and, more particularly, to detection of crystal lattice defects during formation of NPN transistor devices on semiconductor integrated circuit dies of a semiconductor wafer.
Electron beam voltage contrast testing for open and shorted conductors on integrated circuit devices in semiconductor wafers is based on the principle that circuit voltage can be determined by measuring the intensity of secondary electron emission. Typically, an electron beam of low voltage is directed onto a device surface while an electron detector is positioned to collect secondary emitted electrons. Open circuit conductor or nodes will charge to a positive voltage and reduce the intensity of secondary electron emission while short circuit nodes will not charge and will have a higher secondary electron emission. An image of the area of inspection will have brighter spots for open-circuit or isolated nodes and darker spots for shorted nodes.
The present invention is directed to use of passive voltage contrast (PVC) inspection for NPN bipolar transistor structures in integrated circuits. Current manufacturing yield of double polycrystalline silicon (poly) NPN bipolar transistor structure with epitaxial base is dependent on crystal lattice quality. Defects in the epitaxial base create device failures. It is extremely difficult to locate crystal defects using current analytical techniques so that cross-sections of defect areas can be prepared to determine a cause of such defects.
Application of PVC inspection to large scale and ultra large scale integrated circuits has a number of problems. For the common NPN bipolar transistor structure, defects at the emitter-base NP junction are not detectable since the underlying collector-substrate NP junction allows charge to accumulate in the collector and to produce a false positive indication of no defects. Further, the size and density of such devices makes most types of inspection and test procedures impractical.